Project Associate – I (PA-I) Notifications – “Under SURE – SERB Project”
Project Associate – I (PA-I) Application Form – “Under SURE – SERB Project”
JRF Notification-SERB CRG Project
JRF Application-SERB-CRG Project
Project Associate – I/II (PA-I/II) Notifications-“MeitY-C2S Project”
Project Associate – I/II (PA-I/II) Application Form-“MeitY-C2S Project”
The Chaitanya Bharati Institute of Technology (CBIT), Gandipet, Hyderabad – 500075 invites applications for the post of Project Associate – I/II (PA-I/II) to work in a “MeitY-C2S Project”
The appointment is intially for a period of six months and is likely to be extended for the duration of the project depending on the performance. The appointment is purely temporary and does not confer any right whatsoever to claim for absorption into the institution. The Institute shall not have any liability in respect of the continuation of service or otherwise. An undertaking to this effect shall have to be submitted at the time of joining the duty.
Project Title: The Design, Fabrication and Development Silicon Proven IP Core for High Resolution ADPLL (5Years)
| Post | Project Associate – I (PA-I) |
| Essential qualification | 1. Post Graduate/Graduate Degree in Electronics and Communication Engineering or equivalent with first class. preferably in VLSI or related fields. |
| Desirable Qualification | 1. GATE/NET qualified.
2. Experience in Verilog HDL. 3. MATLAB experience 4. Experience in Analog IC Design and Cadence Virtuoso. |
| Pay-per month | Rs. 31,000 + HRA (for GATE/NET qualified) or Rs. 25,000 + HRA (for Others) |
| Age Limit | 35 years (Age Relaxation applicable as per DST norms) |
| Notification | View Details! |
| Application Form | Download! |
| Post | Project Associate – II (PA-II) |
| Essential qualification | 1. Post Graduate/Graduate Degree in Electronics and Communication Engineering or equivalent with first class. preferably in VLSI or related fields.
2. Minimum two (2) years experience in Research and Development (VLSI) |
| Desirable Qualification | 1. GATE/NET qualified.
2. Experience in Verilog HDL. 3. Experience in Analog Design & Cadence Virtuoso. 4. Experience in Custom Layout. 5. Full Custom Tape-out Experience |
| Pay-per month | Rs. 31,000 + HRA (for GATE/NET qualified) or Rs. 28,000 + HRA (for Others) |
| Age Limit | 35 years (Age Relaxation applicable as per DST norms) |
| Notification | View Details! |
| Application Form | Download! |
Duly filled application in the attached format should be mailed with the Subject “Application for the post of PA – I/ PA-II In MeitY-C2S Project” on or before 4:00 P.M of 26th September 2023 (Tuesday) to jahangir_ece@cbit.ac.in (CI) with copy to principal@cbit.ac.in and hr@cbit.ac.in Eligible candidates will be called for Interview and will be informed by email/phone. Self attested Xerox Copies of educational qualifications and experience in support of your claim should be attached to the mail along with the application. The Prescribed qualifications are minimum and the mere fact that a candidate possessing the same will not entitle him/her for being called for written test and interview. The Institution reserves the right to restrict the candidates to be called for interview to a reasonable number on the basis of qualifications and experience higher than the minimum prescribed. The institute also reserves the right either to fill up or not to fill up the posts. For any further queries, please contact to Mr. Mohd Ziauddin Jahangir, Asst. Prof. ECE. (Cell No.9885717845).
The Chaitanya Bharathi Institute of Technology (CBIT), Gandipet, Hyderabad – 500075 invites applications for the post of Junior Research Fellow (JRF) under a CRG-SERB project.